The present invention relates generally to phase locked loop (PLL) circuits. More particularly, this invention relates to a PLL circuit which is based on a voltage controlled differential oscillator and an advanced common biasing technique, which tolerates process variations and calibrates current ranges for operational request frequency that provides frequency stability with temperature change without the use of a bandgap reference bias circuit.
Phase-locked loops are often used in the I/O interfaces of digital integrated circuits in order to hide clock distribution delays and to improve overall system timing. The maintenance of the timing throughout a circuit is important. Timing becomes particularly critical for applications requiring high-speed processing of information, such as with video processors.
The timing throughout a circuit deviates from the system clock when noise is introduced by various system components and as a result of capacitive effects due to system interconnections. In recent years, the demand has risen for devices capable of high-speed processing. As a result, the demand for PLL circuits that quickly compensate for electronic noise and capacitive delays has also risen. The problem is that the amount of phase shift produced as a result of the supply, substrate noise and capacitor load is directly related to how quickly the PLL can correct the output frequency.
One type of design used by those skilled in the art to eliminate the noise present in the circuit at the required speed is a self-bias signal technique. Referring to FIG. 1, this prior art PLL circuit is a self-biasing configuration which is composed of a phase comparator, charge pump, loop filter, bias generator and a voltage-controlled oscillator (VCO). This PLL circuit also uses an additional charge pump current to the bias generator Vbp output. For a typical PLL, the charge pump current and the loop filter resistance are constant. These conditions give rise to a constant damping factor and a constant loop bandwidth. A constant loop bandwidth can constrain the achievement of a wide operating frequency range and low input tracking jitter. If the frequency is disturbed, the phase error that results from each cycle of the disturbance will accumulate for many cycles until the loop can compensate for the frequency error. The error will be accumulated for a number of cycles, which is proportional to the operating frequency divided by the loop bandwidth. Thus the loop bandwidth would have to be positioned as close as possible to the reference frequency bandwidth to minimize the total phase error. The result is that the frequency bandwidth must be conservatively set for stability at the lowest operating frequency with worst case process variations, rather than set for optimized jitter performance. The self-biased PLL also exhibits much faster locking times only when locking from similar or higher operating frequencies. If, however, the self-biased PLL is started at a very low operating frequency, it will exhibit very slow locking times.
Accordingly, there is a need for a PLL circuit that provides a fast lock-up, improved jitter performance, tolerates process variations, and extends the PLL operating frequency range.